AXI-DMA Performance Comparison Between Modes
The way DMA transfers are configured in software can have a significant impact on throughput.
WinDriver’s QA team tested several AXI-DMA configurations using the WinDriver AXI-DMA sample. The objective was to determine which software configuration delivers the best performance under the same hardware conditions.
The comparison focused on three variables:
- Completion method: Polling vs. Interrupts
- Descriptor configuration: Cyclic mode vs. Ping-pong mode
- Driver implementation: Kernel PlugIn (KP) vs. No Kernel PlugIn (KP)
All tests were executed on the same machine to ensure a fair comparison.
Understanding the Test Configurations
| Configuration | Description |
| KP | Cyclic | Kernel PlugIn enabled with cyclic mode |
| KP | Ping-Pong | Kernel PlugIn enabled with ping-pong mode |
| User-mode | Cyclic | User-mode driver with cyclic mode |
| User-mode | Ping-Pong | User-mode driver with ping-pong mode |
Understanding Descriptor Modes
Cyclic Mode: In this mode, the DMA engine continuously cycles through a defined list of descriptors. Once the last descriptor in the chain is processed, the hardware automatically wraps back to the first one. This is ideal for continuous data streaming, as it allows the hardware to operate without needing software to restart the process for each buffer.
Ping-Pong Mode: In this mode, the DMA engine toggles between two dedicated buffer areas (the “ping” and “pong” buffers). While the hardware writes to or reads from one buffer, the software can simultaneously process or prepare the other. This double-buffering approach prevents data overwriting and ensures a continuous flow, though it requires more active software management to switch buffers after each transfer completes.
The Kernel PlugIn (KP) executes performance-critical operations in kernel space, reducing software overhead. The descriptor sets define how DMA transfer descriptors are managed, with cyclic and ping-pong modes determining how the hardware cycles through buffer descriptors.
Test 1 – Host-to-Device Using Polling
The first test measures Host-to-Device transfers using polling as the completion method.
Several observations stand out:
- Kernel PlugIn with cyclic mode consistently delivers the highest throughput.
- Using cyclic mode significantly outperforms ping-pong mode.
- Even without Kernel PlugIn, reducing descriptor overhead noticeably improves performance.
These results show that minimizing software overhead allows the DMA engine to dedicate more time to moving data instead of managing descriptors.
Test 2 – Device-to-Host Using Polling
The Device-to-Host polling benchmark follows the same pattern.
Again:
- KP | Cyclic achieves the highest transfer rates.
- Cyclic mode consistently outperforms ping-pong mode.
- Throughput increases with larger buffer sizes before reaching a plateau.
The consistency between transmit and receive directions demonstrates that the performance gains are not workload-specific.
Test 3 – Host-to-Device Using Interrupts
Interrupt-based transfers show a different performance profile.
Compared to polling:
- Overall throughput is lower.
- Kernel PlugIn still provides a substantial improvement.
- Interrupt handling introduces additional overhead that limits maximum bandwidth.
Interrupt mode remains valuable for applications where CPU efficiency and asynchronous operation are more important than absolute throughput.
Test 4 – Device-to-Host Using Interrupts
The final test confirms the same trend for Device-to-Host transfers.
Kernel PlugIn continues to improve throughput, while interrupt processing limits peak bandwidth compared to polling.
Across all four tests, the observed behavior remains remarkably consistent.
Why Does Polling Perform Better?
DMA transfers move data independently of the CPU. However, once a transfer completes, the CPU must be notified.
There are two common completion methods:
- Polling, where software continuously checks DMA status.
- Interrupts, where the DMA engine signals the CPU when the transfer finishes.
Polling avoids interrupt generation, context switching, and interrupt service routine overhead. In the tested AXI-DMA implementation, ping-pong mode also requires maintaining two descriptor sets, adding further management overhead compared to the streamlined cyclic mode.
Key Takeaways
Our tests provide several practical recommendations for developers working with AXI-DMA:
- Polling delivers the highest throughput when maximum transfer performance is the priority.
- Cyclic mode performs better than ping-pong mode in polling mode.
- Kernel PlugIn significantly improves performance across all tested scenarios.
- 4-byte memory alignment remains an important optimization for efficient DMA transfers.
Conclusion
The results demonstrate that DMA performance depends not only on the hardware IP but also on driver architecture and software configuration.
For developers using WinDriver with AXI-DMA, selecting the appropriate completion method, minimizing descriptor overhead, and leveraging the Kernel PlugIn can provide measurable throughput improvements without requiring any hardware changes.
