| Enumerator |
|---|
| PCI_VID | Vendor ID.
|
| PCI_DID | Device ID.
|
| PCI_CR | Command register.
|
| PCI_SR | Status register.
|
| PCI_REV | Revision ID.
|
| PCI_CCR | Class code.
|
| PCI_CCSC | Sub class code.
|
| PCI_CCBC | Base class code.
|
| PCI_CLSR | Cache line size.
|
| PCI_LTR | Latency timer.
|
| PCI_HDR | Header type.
|
| PCI_BISTR | Built-in self test.
|
| PCI_BAR0 | Base address register.
|
| PCI_BAR1 | Base address register.
|
| PCI_BAR2 | Base address register.
|
| PCI_BAR3 | Base address register.
|
| PCI_BAR4 | Base address register.
|
| PCI_BAR5 | Base address register.
|
| PCI_CIS | CardBus CIS pointer.
|
| PCI_SVID | Sub-system vendor ID.
|
| PCI_SDID | Sub-system device ID.
|
| PCI_EROM | Expansion ROM base address.
|
| PCI_CAP | New capability pointer.
|
| PCI_ILR | Interrupt line.
|
| PCI_IPR | Interrupt pin.
|
| PCI_MGR | Minimum required burst period.
|
| PCI_MLR | Maximum latency - How often device must gain PCI bus access.
|
Definition at line 29 of file pci_regs.h.
1.9.7