mSGDMA Intel FPGA IP with WinDriver

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In embedded systems and FPGA applications, efficient data transfer is crucial.

mSGDMA Intel FPGA IP provides high-speed memory-to-memory transfers, enabling optimized Direct Memory Access (DMA) operations. Paired with WinDriver, Jungo’s driver development toolkit, it simplifies the integration process. Together, they offer a flexible, scalable, and cross-platform solution for developers working with Intel FPGAs.


What is mSGDMA Intel FPGA IP?

mSGDMA Intel FPGA IP is a key IP core for Intel FPGAs, designed to perform DMA operations. It allows data to move directly between memory and peripheral devices, bypassing the CPU. This reduces CPU load, making it ideal for high-throughput tasks, such as video processing and network communications. It ensures data is transferred efficiently in real-time applications, such as high-speed data acquisition.

The mSGDMA Intel FPGA IP simplifies hardware communication, but integrating it into a complete system can be challenging. WinDriver makes this process easier by providing a user-mode API allowing kernel mode development and debugging. With WinDriver, developers can focus on application logic rather than dealing with complex kernel development.


Workflow for mSGDMA with WinDriver

Configure mSGDMA Intel FPGA IP

This step involves configuring the mSGDMA IP core to match your system requirements, including the number of DMA channels and memory parameters.

  • Use Intel tools (Quartus Prime/Platform Designer) to add and configure the mSGDMA Intel FPGA IP core.

  • Set the DMA parameters (e.g., data width, burst length, channels) based on your system requirements.

  • Generate the register map and address map for the DMA configuration.

 

Install WinDriver

In this step, you’ll install WinDriver on the target system and initialize the API to enable communication with the hardware.

  • Install WinDriver on the target system (Windows/Linux).

  • Open the DriverWizard to simplify the driver creation process.

  • Select and open the device in the DriverWizard.

  • Use the GUI to configure device parameters, such as memory mapping, DMA settings, and other required settings.

  • Generate the driver code based on the configured parameters.

  • Customize the generated code to fit your specific design needs and build it.

 

Allocate and Lock DMA Buffers

This step allocates memory buffers for DMA transfers and locks them in physical memory to ensure they remain accessible during the transfer.

  • Use WinDriver’s API to allocate memory buffers for DMA transfers.

  • Lock the buffers in physical memory to ensure they are accessible by the DMA controller.

 

Configure DMA Transfer

Set up the DMA transfer parameters, including the direction of the transfer and the size of the data to be moved.

  • Set the DMA direction (host-to-device or device-to-host) and transfer size using WinDriver’s API.

  • Configure other DMA parameters as needed (e.g., burst length).

 

Handle Interrupts

Set up interrupt handling to monitor the progress of the DMA transfer and manage any errors or completion notifications.

  • Set up interrupt handling to monitor the progress of the DMA transfer.

  • Handle any errors or status changes during the transfer (e.g., completion or failure).

​​

Release Resources

Once the DMA transfer is complete, release allocated buffers and clean up any resources used during the process.

  • After the transfer completes, use WinDriver’s API to unmap and release DMA buffers.

  • Clean up any resources, disable interrupts, and shutdown the WinDriver environment.

 

Benefits

Seamless Integration

WinDriver simplifies the process of initializing and configuring the mSGDMA Intel FPGA IP core. The integration is straightforward and avoids the need for manual register-level programming.

Cross-Platform Compatibility

WinDriver is designed to work across multiple platforms, including Windows, Linux, and MacOS. This ensures that the same driver can be deployed on different operating systems without modifications.

Simplified DMA Buffer Management

Managing DMA buffers can be tricky, but WinDriver makes it easier. It offers functions to allocate, lock, and unlock memory buffers, ensuring that the mSGDMA IP core can access them during the transfer.

Efficient Transfer Configuration

Configuring DMA transfers is essential for high-performance systems. With WinDriver, this process becomes straightforward. You can configure DMA transfer direction, size, and initiate the transfer with a few function calls.

Interrupt Handling and Transfer Completion

Interrupts are crucial for monitoring DMA transfers. WinDriver provides robust interrupt handling, notifying you when the transfer is complete or when errors occur.

Flexibility and Customization

WinDriver offers flexibility for customization. While it provides a simple and efficient way to develop DMA drivers, it also supports modifications and extensions. If needed, you can add custom functionality to meet specific requirements.

Intel® Stratix® 10 GX

A flagship platform for high-performance designs, including data center acceleration, AI/ML workloads, and real-time signal processing. Fully supports Avalon-MM DMA IP via Qsys.
FPGA Device: 1SG280LU2F50E2VG
2.8 million logic elements (LEs), 229 Mb of M20K memory
PCIe Interface: PCIe Gen3 x16 (hard IP)
Supports DMA to/from host system memory at high throughput
Memory:
2 × 8 GB DDR4 DIMMs, 72-bit (ECC) with ~25.6 GB/s bandwidth
Transceivers & Expansion:
Up to 96 transceivers @ 17.4 Gbps

Intel® Cyclone® 10 GX

A lower-cost solution that still supports Avalon-MM DMA flows via PCIe. Suitable for industrial, medical, and IoT applications where power and cost matter.
FPGA Device: 10CX220YF780E5G
220K LEs, 13 Mb embedded RAM, 154 DSP blocks
PCIe Interface: PCIe Gen2 x4
Supported via Avalon-MM Qsys integration
Memory:
2 × 2 GB DDR3 SDRAM (32-bit interface)
Expansion:
HSMC connector, GPIO headers, transceiver SMA connectors

Intel® Arria® 10 GX

Arria 10 devices balance high performance and power efficiency, ideal for mid-range applications like broadcast, wireless, and test equipment.
Process Technology:
20nm
Logic Density:
Up to 1.5 million logic elements
DSP Capabilities:
Integrated hardened floating-point DSP blocks
Interface Support:
PCIe Gen3, 10/40/100G Ethernet, DDR4
Full Benefits
Guidance
Features
Technical Data

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