Jungo’s WinDriver offers native support for Xilinx’s QDMA IP, and provides a ready-to-use sample project to accelerate driver development on both Windows and Linux platforms. This guide walks you through compiling, customizing, and extending the WinDriver QDMA IP sample.
QDMA Architecture Overview
The Xilinx QDMA architecture is designed to support high-throughput, low-latency data transfers between host memory and FPGA logic using a scalable, queue-based interface. Unlike traditional DMA engines, QDMA enables the host to manage DMA transactions directly through descriptor rings, supporting thousands of queues with independent flow control. This makes it ideal for applications like SmartNICs, storage acceleration, and data center workloads, where parallelism and host-driven scheduling are critical.
Performing DMA Transactions
The diagnostic utility enables users to perform Direct Memory Access (DMA) transactions by adding and starting Memory-Mapped (MM) queues, and creating read or write requests. Users can choose between blocking and non-blocking methods to view transaction details, including transaction rates. It also supports access to QDMA’s indirect context registers, allowing the host application to read or modify queue descriptors, completion ring state, and credit counters through a unified high-level API.
What’s Included in Sample?
The QDMA sample provided with WinDriver includes a working demonstration of how to interface with the Xilinx QDMA IP core using WinDriver’s high-level C API. The sample contains the following files:
-
qdma_diag.c: The entry point of the application, demonstrating QDMA functionality using the helper library.
-
qdma_lib.c: Implements reusable functions for accessing the QDMA IP through WinDriver’s API.
-
CMakeLists.txt: A build configuration script for CMake.
-
readme.pdf: Documentation describing how to compile and extend the sample.
The sample is implemented as a console-mode application using standard input/output for user interaction. However, it can easily be converted to a GUI-based application if needed.
Step by Step Guide
Control Register Bit Management
QDMA relies on a set of control and status registers to manage both Host-to-Card (H2C) and Card-to-Host (C2H) operations.
- Control Register Addressing: Define and map the control register space using the proper BAR (Base Address Register).
- Bit Masks: Use well-defined bit masks to control operations such as enabling queues, starting DMA, stopping a queue, and enabling interrupts.
- Status Monitoring: Use status registers to check DMA progress, queue activity, and to detect errors.
Tip: QDMA’s context management may involve indirect access registers to configure queue parameters.
Mapping Register Offsets
Each block in the QDMA IP core uses predefined offsets for its control functionality:
- H2C/C2H Queue Control and Status Registers: Used to initiate and monitor DMA transfers for specific queues.
- Configuration and Capability Registers: Provide the interface to configure number of queues, descriptor sizes, and performance modes.
- Interrupt Registers: Enable, clear, and monitor MSI/MSI-X interrupts.
Ensure that BAR scanning is done correctly using WinDriver’s diagnostic library (wdc_diag_lib.c) to access the correct register sets.
DMA Buffer Allocation and Locking
QDMA supports scatter-gather and contiguous buffer modes. With WinDriver:
- Use
WDC_DMASGBufLockfor scatter-gather DMA. - Use
WDC_DMAContigBufLockfor descriptor and status buffers.
DWORD descSize = NUM_DESCRIPTORS * sizeof(QDMA_DESCRIPTOR);
PVOID pDescBuf = NULL;
PHYSICAL_ADDRESS descPhysAddr;
BOOL result = WDC_DMAContigBufLock(hDev, &pDescBuf, &descPhysAddr, descSize, DMA_TO_DEVICE);
if (!result) {
printf("Failed to lock descriptor buffer\n");
return;
}Ensure the descriptor buffer is aligned and preloaded with valid descriptors according to QDMA’s ring format.
Setting Up QDMA Descriptors
QDMA uses a ring-based descriptor format. Each descriptor must contain:
- Source/Destination Address
- Length
- Flags (e.g., EOP – End of Packet)
- Next descriptor pointer (if using linked list)
Descriptors are placed into ring buffers, which the FPGA accesses via physical addresses.
Writing Queue Context to Device
To enable a queue:
- Write to QDMA’s Queue Context Region using indirect context access registers.
- Configure:
- Queue type (memory-mapped or streaming)
- Descriptor base address and size
- Completion queue (if used)
Use WinDriver APIs to map the indirect access interface and update queue contexts.
Triggering DMA Transfer
- H2C Transfer:
- Host writes payload to buffer.
- Notifies FPGA via a doorbell register or context update.
- C2H Transfer:
- FPGA writes to host memory.
- Host polls or waits for interrupt.
Registers are written using WinDriver’s WDC_WriteAddr32 or WDC_WriteAddr64 to mapped BAR space.
Interrupt Handling
QDMA supports both polling and MSI/MSI-X interrupt modes. WinDriver supports registration of interrupt handlers:
BOOL result = WDC_IntEnable(hDev);
if (!result) {
printf("Failed to enable interrupts\n");
}Interrupt handlers in WinDriver are used to track transfer completion, queue activity, or errors.
Cleanup and Resource Management
Once transfers are complete:
- Call
WDC_DMABufUnlockto release locked memory. - Reset the queue or disable it by clearing its context.
- Release the device handle and free resources.
Common Use Cases for QDMA
Network Function Virtualization (NFV)
QDMA allows rapid movement of packets between host memory and FPGA-based acceleration functions for virtual switches, firewalls, and routers.
SmartNICs / DPUs
FPGAs with QDMA can act as intelligent network adapters capable of inline processing, filtering, and packet forwarding with minimal CPU overhead.
High-Performance Storage (NVMe/RDMA)
QDMA supports low-latency access and multi-queue IO pipelines — ideal for FPGA-based NVMe controllers or storage front-ends.
Financial Trading Systems
Enables ultra-low latency access between CPU and custom trading logic running on the FPGA.
Custom Accelerators (AI/ML, Compression, Encryption)
QDMA efficiently feeds high-throughput data into custom logic (e.g., CNN layers, AES cores) with deterministic performance.
Embedded Test Equipment / Instrumentation
Supports precise data capture and transmission between instruments and host systems over PCIe with multi-channel queues.
User-mode driver development
WinDriver enables safe and efficient driver development entirely in user space, eliminating the need to write or debug kernel-mode code.
Cross-platform compatibility
Applications built with WinDriver are portable across major operating systems, allowing unified driver logic and faster cross-platform deployment.
Ready-to-use diagnostics tools
The SDK includes modular diagnostics libraries and utilities that simplify hardware access, testing, and integration during development.
Fast prototyping
Developers can rapidly prototype high-performance drivers with direct access to key PCIe hardware interfaces such as DMA, IRQs, and BARs.
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