Altera PCIe Hard IP for Avalon-MM Interface

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For high-performance FPGA-based systems, Direct Memory Access (DMA) is essential.

Avalon-MM is a standard interface for memory-mapped transactions in Intel's Platform Designer (formerly Qsys) system integration tool. When paired with a robust software framework like Jungo WinDriver, developers can streamline PCIe-connected FPGA DMA operations on Windows and Linux hosts.


Avalon-MM Interface

Intel FPGAs, spanning the Stratix, Agilex, and Arria families, enable high-performance data movement through Direct Memory Access (DMA) when paired with the Avalon Memory-Mapped (Avalon-MM) interface. Avalon-MM is a well-established standard for internal memory-mapped communication in Intel-based designs and plays a central role in connecting custom logic to external memory and high-speed interfaces such as PCIe.

When DMA is implemented over Avalon-MM, it allows for efficient, sustained data throughput between the host and FPGA logic, suitable for workloads such as sensor ingest, packet processing, video frame buffering, and machine learning acceleration. However, the software driver stack traditionally needed to control such designs can be both time-consuming and platform-specific.

Jungo WinDriver offers an ideal solution for developers looking to bypass the complexity of writing kernel-mode drivers and get direct access to DMA operations in user mode. By supporting Windows, Linux, and ARM platforms, WinDriver brings cross-platform consistency and accelerates development across a range of host environments.

 

Streamlined Integration

Using the Avalon-MM DMA interface within Intel FPGAs involves configuring your hardware to handle Host-to-Card (H2C) and Card-to-Host (C2H) communication. This typically involves setting up descriptor-based memory transfers between host RAM and the FPGA’s memory-mapped logic.

With Jungo’s Avalon-MM DMA samples, developers benefit from:

  • Pre-defined code structures for buffer setup, descriptor management, and register interaction
  • Built-in support for memory locking, DMA mapping, and user-mode interrupt handling
  • Simplified access to PCIe Base Address Registers (BARs) and control/status regions

This high level of abstraction significantly reduces onboarding time and removes the need for deep familiarity with operating system kernel development.

 

A Flexible, Multi-Platform Development Model

One of WinDriver’s standout strengths is its platform agnosticism. Developers can begin working on a Windows workstation, then migrate their application to a Linux server or an embedded ARM-based system with minimal code changes. The same user-mode API, DMA buffer handling, and BAR access routines apply across all supported OS targets.

This flexibility is especially valuable for teams building production solutions where development may occur on one OS, but deployment occurs on another. With WinDriver, you maintain consistency and efficiency throughout.


Implementation Steps

Design Your Avalon-MM DMA Hardware Subsystem

Use Platform Designer (Qsys): Create a new system in Intel’s Platform Designer and instantiate the following IP components:

  • PCIe Hard IP for Intel FPGA (or Soft IP for earlier devices)
  • Avalon-MM DMA Controller
  • Avalon-MM Bridge Interfaces (clock crossing or width adapters as needed)
  • On-chip Memory or External Memory Controller (EMIF)
  • Interrupt Sender (optional)

Assign Base Addresses: Define base addresses for the DMA controller, descriptor buffer, and status registers in the Address Map window.

Generate HDL: Export the Qsys-generated HDL and integrate it into your top-level Quartus project. Synthesize and compile the design.

​​

Generate PCIe BAR and Register Map

Define BARs: Assign memory regions for the DMA controller and descriptors to PCIe Base Address Registers (BARs). For example:

  • BAR0: Control/status registers
  • BAR2: DMA descriptor memory region

Export Register Map: Note register offsets for:

  • Descriptor base address
  • Transfer length
  • Start/Stop flags
  • IRQ enable/status flags

This information is critical for the software layer to control the DMA engine.

​​

Write a WinDriver-Based Software Application

With your FPGA bitstream ready and PCIe enumeration configured, use Jungo WinDriver to control the DMA from the host side.

Detect the FPGA Device

Use WDC_PciScanDevices() or DriverWizard to find the FPGA based on vendor/device ID. Open a handle to the device.

hDev = WDC_DeviceOpen(...);

Map BARs and Set Pointers

Use WDC_MemMap() to map BARs for register access. Define pointers to control registers, descriptor regions, and status flags.

WDC_MemMap(hDev, 0, &pBar0); // Control
WDC_MemMap(hDev, 2, &pDescBuf); // Descriptors

​​

Allocate and Lock DMA Buffers

Allocate a buffer in user space using malloc(), then lock it for DMA using:

WDC_DMASGBufLock(hDev, &pBuf, &dmaAddr, size, DMA_TO_DEVICE);

This provides:

  • Virtual address for CPU access
  • Physical address for FPGA use

You must also prepare the descriptor ring that points to these addresses.

 

Configure DMA Descriptors

Each descriptor typically includes:

  • Source address (H2C) or destination (C2H)
  • Transfer length
  • Control flags (start, EOP)

Write descriptors to the mapped descriptor memory using memcpy() or WDC_WriteAddr32() depending on access type.

​​

 Start the DMA Transfer

Use WinDriver to write control values to the DMA start register. For example:

WDC_WriteAddr32(hDev, TRANSFER_BAR, DMA_CONTROL_OFFSET, DMA_START_BIT);

Optional: Enable interrupts for completion notification.

​​

Monitor Transfer Status

You can choose between:

  • Polling: Read the DMA status register until a done flag is set
  • Interrupts: Register an ISR using WDC_IntEnable()

In the interrupt handler, check the IRQ source and acknowledge the interrupt by clearing the status bit.

​​

Post-Transfer Actions

After DMA completes:

  • Use the dmaAddr mapping to verify transfer integrity
  • Unlock the buffer with WDC_DMABufUnlock()
  • Optionally reset DMA engine registers

You can now repeat the process or close the connection cleanly.

 

Debugging Tips

  • Use SignalTap II logic analyzer for real-time probing of DMA signals
  • Check PCIe link status in Quartus Programmer or Linux lspci
  • Confirm BAR sizes and memory maps match between Qsys and software

​​

Benefits

Rapid Development

Accelerates the development cycle by providing ready-to-use driver frameworks.

Stability and Safety

Operating in user mode reduces the risk of system crashes due to driver errors.

Comprehensive Support

Backed by detailed documentation and a responsive support team to assist with development challenges.

Flexibility

Supports a wide range of devices and can be adapted to various FPGA configurations.

Altera Innovation


In a world of endless opportunities and challenges, Altera is here to provide the flexibility to pioneer and accelerate innovation.

Intel® Stratix® 10 GX

A flagship platform for high-performance designs, including data center acceleration, AI/ML workloads, and real-time signal processing. Fully supports Avalon-MM DMA IP via Qsys.
FPGA Device: 1SG280LU2F50E2VG
2.8 million logic elements (LEs), 229 Mb of M20K memory
PCIe Interface: PCIe Gen3 x16 (hard IP)
Supports DMA to/from host system memory at high throughput
Memory:
2 × 8 GB DDR4 DIMMs, 72-bit (ECC) with ~25.6 GB/s bandwidth
Transceivers & Expansion:
Up to 96 transceivers @ 17.4 Gbps

Intel® Cyclone® 10 GX

A lower-cost solution that still supports Avalon-MM DMA flows via PCIe. Suitable for industrial, medical, and IoT applications where power and cost matter.
FPGA Device: 10CX220YF780E5G
220K LEs, 13 Mb embedded RAM, 154 DSP blocks
PCIe Interface: PCIe Gen2 x4
Supported via Avalon-MM Qsys integration
Memory:
2 × 2 GB DDR3 SDRAM (32-bit interface)
Expansion:
HSMC connector, GPIO headers, transceiver SMA connectors

Intel® Arria® 10 GX

Arria 10 devices balance high performance and power efficiency, ideal for mid-range applications like broadcast, wireless, and test equipment.
Process Technology:
20nm
Logic Density:
Up to 1.5 million logic elements
DSP Capabilities:
Integrated hardened floating-point DSP blocks
Interface Support:
PCIe Gen3, 10/40/100G Ethernet, DDR4
Faster Development with Pre-Integrated Qsys + PCIe + DMA Examples
WinDriver IP samples include pre-built driver code aligned with Intel’s Platform Designer (Qsys) and Avalon-MM DMA IP. This allows developers to bypass low-level PCIe register configuration and start transferring data within hours, not weeks.
Seamless User-Mode Driver Development for Avalon-MM Designs
The IP samples enable full user-mode driver implementation, eliminating the need to write or debug fragile kernel code. This improves safety and accelerates debugging, as crashes in user-mode do not affect the entire system.
Cross-Platform Support for Intel-FPGA-Based Systems
Jungo WinDriver supports development on Windows, Linux x86, and Linux ARM, making the same IP samples usable across desktop, industrial, and embedded environments without rewriting OS-specific code.
Built-in PCIe BAR Access, Avalon-MM DMA, and Interrupt Support
The samples include tested implementations of BAR memory mapping, Avalon-MM DMA setup, and MSI/MSI-X interrupt handling. This allows immediate evaluation of FPGA-to-host and host-to-FPGA data transfers using Intel’s PCIe endpoint.
Integrated with DriverWizard for Intel PCIe Devices
All samples are compatible with Jungo’s DriverWizard, enabling automatic code generation for Intel FPGA devices. Developers can quickly scan the PCIe configuration space, map BARs, and insert DMA logic with minimal manual intervention.
Proven Foundation for Production and Certification
The WinDriver samples provide a stable reference for passing formal driver testing (e.g., HLK for Windows or Linux LTP). They also reduce debugging time by serving as a known-good baseline when integrating Avalon-MM or custom IPs.
Full Benefits
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