As a trusted Lattice partner, Jungo WinDriver offers ready-to-use drivers and DMA sample projects for Avant and CPNX FPGAs. These eliminate the need for custom driver development, helping engineers save time. You can either access these samples from the sample folder or generate them using the DriverWizard.
Understanding the Lattice DMA Workflow
The WinDriver Lattice DMA samples sequence involves:
- Creating Memory Buffers for Data and Descriptors
- Configuring the Descriptor Buffer
- Writing Descriptor Address to the Device
- Initiating the DMA Transfer
- Data Transfer Execution
- Completion and Interrupt Handling
- Cleanup (DMA Close Routine)
Let’s break down each step in detail.
Lattice DMA Workflow
Step 1: Creating Memory Buffers for Data and Descriptors
Before transferring data, memory must be allocated and locked to ensure stability.
The DMA in CPNX requires two types of buffers:
- Data Buffers – Store actual transfer data.
- Descriptor Buffers – Contain metadata such as transfer length and addresses.
Avant DMA required a third type of buffers for the Status, which is stored on the device in CPNX.
Allocating Buffers for the DMA
Using these functions:
- WDC_DMASGBufLock → locks a pre-allocated user-mode memory buffer for the data buffers and returns the corresponding physical mappings of the locked DMA pages.
- WDC_DMAContigBufLock → Allocates a contiguous buffer for the descriptor, locks it in physical memory, and returns mappings of the allocated buffer to physical address space and to user-mode and kernel virtual address spaces.
Allocating & Locking the Memory for the Data
💡 Tip: Avant FPGAs also require a status buffer.
Step 2: Configuring the Descriptor Buffer
Once memory is allocated, descriptors must be set up to define:
- Source and destination addresses
- Transfer length
- Next descriptor address (for chained transfers)
How to Set Up Descriptors
Using the function:
DmaTransferBuild → prepares a list of instructions for the DMA engine to efficiently move data between the CPU and FPGA without involving the processor directly.
Step 3: Writing Descriptor Address to the Device
After descriptor configuration, the descriptor addresses are written to the FPGA. This enables the device to fetch metadata when needed.
Using the function:
- WriteDescriptorsDataToCPNX → configures the FPGA by writing DMA descriptor addresses and counting into its registers so that it knows where to find the descriptors for the data transfer.
💡 Tip: If you’re using Avant, you must also configure the status buffer.
Step 4: Initiating the DMA Transfer
To begin data transfer, the host writes to a specific offset on the FPGA.
How to Start the Transfer
Use the function:
CPNX_DMA_StartDMA → Initiates DMA transaction.
Step 5: Data Transfer Execution
Once started, the FPGA reads the descriptor buffer to fetch the source and destination addresses and moves data accordingly.
How it works:
- First descriptor fetches the first data buffer.
- Upon completion, the next descriptor is processed.
- This continues until the last descriptor is reached.
Step 6: Completion and Interrupt Handling
When the last descriptor finishes transferring data:
- An interrupt is raised, notifying the CPU of completion.
Polling vs. Interrupt-Driven DMA
- Polling: CPU constantly checks if DMA is done (inefficient).
- Interrupt-Driven DMA: FPGA notifies CPU via an interrupt (preferred).
💡 In may cases Interrupt-driven DMA is more efficient as it reduces CPU workload.
Step 7: Cleanup (DMA Close Routine)
After completion, buffers are unlocked, and memory is freed to prepare for the next transfer.
💡 Note: CPNX FPGAs don’t have a built-in stop function, so the cleanup routine is essential.
Performance Boost: Using the Kernel Plugin
The kernel plugin significantly improves DMA performance by reducing CPU context switching.
Performance Test Results:
- Kernel plugin improves DMA speed by 100%+ in some cases.
- Lower CPU overhead and faster transfer rates.
- Works automatically—no additional code is required.
CertusPro-NX (CPNX)
10G SERDES at Lowest Power and Smallest Package
Up to 8 SERDES lanes supporting up to 10.3 Gbps per lane, in packages as small as 9x9 mm. Up to 4x lower power vs. similar FPGAs
More On-chip Memory, and LPDDR4 Support – Up to 7.3 Mb of on-chip memory
Up to 7.3 Mb of on-chip memory. Only FPGA in class with LPDDR4 support. LPDDR4, DDR3/3L, LPDDR2 supported at 1066 Mbps.
Built on Lattice Nexus platform – Class-leading power efficiency.
Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.
High Logic Density in a Small Footprint
Offers high logic density, enabling designers to integrate more functionality into a single device without increasing board space.
Avant™-E
Mid-range FPGA Family
AvantE belongs to the mid-range class of FPGAs, striking an ideal balance between performance, power efficiency, and cost.
Optimized for Lowest Power and Highest Performance
AvantE is architected from the ground up to deliver class-leading performance per watt.
Industry-Leading DSP and Embedded Memory to Logic Ratio
AvantE delivers the highest DSP and embedded memory to logic ratio among mid-range FPGA offerings.
Fast External Memory Support
AvantE includes robust support for high-speed external memory interfaces, including LPDDR4 and DDR4 running at up to 1866 Mbps.
Faster Development with Pre-Integrated Code
WinDriver IP samples come with ready-to-use driver code that is already tailored for Lattice devices, significantly accelerating the initial development phase and reducing the need to write low-level hardware access logic from scratch.
Seamless User-Mode Driver Support
The samples enable user-mode driver development, eliminating the need to write complex kernel-mode code. This improves system stability and allows quicker debugging without the risk of system crashes.
Cross-Platform Compatibility
WinDriver supports development on Windows, Linux, and Linux ARM platforms, making the IP samples usable across a wide range of embedded and desktop systems without rewriting code for each OS.
Built-in Support for PCIe, DMA, and Interrupts
The samples include robust handling of PCIe interfaces, Direct Memory Access (DMA), and hardware interrupts, offering a complete framework to test and integrate high-speed communication between the Lattice FPGA and host processor.
DriverWizard Integration for Auto-Generated Code
The IP samples work seamlessly with Jungo’s DriverWizard, allowing developers to auto-generate customized driver code for their Lattice design, minimizing manual errors and boosting productivity.
Reliable Reference for Certification and Debugging
These samples serve as tested, reliable reference implementations that can help pass driver certification (e.g., WHQL on Windows) and reduce time spent troubleshooting driver-hardware communication issues.
Full Benefits
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